Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers

This brief proposes a fully dynamic discrete-time ${\Delta }{\Sigma }$ ADC using closed-loop two-stage cascoded floating inverter amplifiers (FIA). The proposed FIA uses non-cascoded as the notation="LaTeX">$1^{\mathrm{ st}}$ stage and one 2 notation="LaTeX">$^{\mathrm{ nd}}$ . By this arrangement well applying metal-insulator-metal (MIM) capacitors for reservoir capacitors, it stably achieves high gain even with input common-mode voltage fluctuation without an additional CMFB nor calibrations. fabricated in 65nm standard CMOS process realizes operation calibration 88.5dB SNDR, 97.9dB SFDR OSR of 256. It consumes 43.5 notation="LaTeX">${\mu }\text{W}$ from 1V supply at 10MHz sampling frequency.